A pseudo-SRAM has been known, which has a basic element of DRAM and is configured to be so operated as SRAM. The pseudo-SRAM is non-synchronous in view of the specification, which is similar to the conventional SRAM. The pseudo-SRAM is configured to have a basic element of DRAM. The pseudo-SRAM is so configured that operations such as refresh being unique to DRAM are automatically performed by the inside thereof.
An example of the conventional non-synchronous semiconductor memory device configured to have a basic element of DRAM will hereinafter be described.
FIG. 13 shows an example of a configuration of the semiconductor memory device of this type. In this drawing, an address ADD is a signal given from the outside, and includes a row address designating a row of a memory cell array to be described below and a column address designating a column thereof.
An address input system 1 latches the address ADD and outputs an internal address LADD. An address transition detector circuit (ATD) 2 detects a transition of the internal address LADD and outputs a one-shot pulse signal OSP. An address multiplexer (MUX) 3 outputs, as an address MADD, any one of the internal address LADD and a refresh address RADD to be described below.
A row decoder 60 decodes the address MADD for selecting a row of a memory cell array 70. The memory cell array 70 comprises a matrix array of memory cells similarly to the general-purpose DRAM. A sense amplifier 71 amplifies a data signal on a bit line for a read operation. A column decoder 72 selects a column of the memory cell array 70. A pre-charge circuit (not illustrated) for bit lines is provided accompanying to the sense amplifier 71.
A refresh timer circuit 8G times a refresh time interval A refresh control circuit 8H controls a series of refresh operations and generates a refresh control signal REFA for controlling a refresh timing accompanying to an external access and a refresh control signal REFB for controlling a self-refresh dining.
A refresh address generator circuit 8J generates an address RADD (hereinafter referred to as “refresh address”) to be used for a refresh operation. An internal pulse generator circuit 10 generates a row enable signal RE, a sense amplifier enable signal SE, a pre-charge enable signal PE and a column enable signal CE.
Other than the above-described circuits, there are further provided a system of circuits for controlling read and write operations, another system of circuits for generating a substrate potential of the memory cell array and still another system of circuits for read and write operations of data to the memory cell array.
The read and write operations and the refresh operation of the semiconductor memory device of the prior art shown in FIG. 13 will sequentially be described with reference to a timing chart of FIG. 14.
A. Read and Write Operations
A read operation according to an address access will be described as one example. In this case, a chip select signal /CS and an output enable signal /OE are set at a low level, while a write enable signal /WE is set at a high level, wherein the address ADD is applied from the outside in accordance with the specification.
The address ADD is taken through the address input system 1 as the internal address LADD. Except for the refresh, this internal address LADD is supplied as the address MADD through the multiplexer 3 to the row decoder 60. At a timing defined by the row enable signal RE, the row decoder 60 selects one word line in the memory cell array 70. Upon selection of the word line, data of memory cells connected to this single row of this word line are read out onto respective bit lines. These data are amplified by the sense amplifier 71 at a timing defined by the sense amplifier enable signal SE.
On the other hand, based on a column address (not illustrated) included in the address ADD, and at a timing defined by the column enable signal CE, the column decoder 72 selects a bit line of the memory cell array 70, so that data on this bit line are supplied through the data output circuit system not illustrated to the outside. Prior to the operation of reading data from the memory cells, bit lines are pre-charged based on the pre-charge enable signal PE
In the above-described series of read operations, upon a transition of the internal address LADD, the address transition detector circuit (ATD) 2 detects this transition of the internal address LADD and outputs a one-shot pulse signal OSP. By triggering this one-shot pulse signal OSP, the internal pulse generator circuit 10 outputs, at appropriate timings, the above-described row enable signal RE, the sense amplifier enable signal SE, the pre-charge enable signal PE and the column enable signal CE.
B. Refresh Operation (in Read Mode)
A refresh operation in a read mode will subsequently be described with reference to a ting chart shown in FIG. 14(a).
In the read mode, the semiconductor memory device according to this conventional technique shows a sequential performance of both the refresh operation and the read operation in the same cycle in accordance with the specification.
The address input system 1 latches an address A0 given from the outside as the address ADD and then outputs the internal address LADD. The address transition detector circuit 2 detects a transition of the internal address LADD and outputs the one-shot pulse signal OSP.
Upon receipt of the one-shot pulse signal OSP, the refresh control circuit 8H starts the refresh operation. Upon the start of the refresh operation, the refresh address generator circuit 8J generates and outputs a refresh row address R0 as the refresh address RADD. Under the control of the refresh control circuit 8H, the address multiplexer 3 supplies the refresh address RADD (the refresh Tow address R0) as the address MADD to the row decoder 60.
On the other hand, the internal pulse generator circuit 10 receives an input of the refresh control signal REFB from the refresh control circuit 8H, and outputs the row enable signal RE and the sense amplifier enable signal SE. The row decoder 60 receives inputs of the address MADD and the row enable signal RE and selects a word line designated by the refresh row address R0 for a predetermined time period defined by the row enable signal RE Data signals of the memory cells connected to the selected word line are amplified by the sense amplifiers and then re-stored therein, whereby the data of the memory cells for the single row designated by the refresh row address R0 have been refreshed.
After the refresh operation has been finished for the row designated by the refresh row address R0, then the read operation is made in the same cycle. For example, the address multiplexer 3 receives the internal address LADD from the address input system 1 and supplies the internal address LADD as the address MADD to the row decoder 60. The row decoder 60 selects the word line designated by the row address R0 included in the input address MADD. The sense amplifier 71 amplifies the data signal appearing on the bit line in the memory cell array 70, so that these amplified data are read out.
C. Refresh Operation (in Stand-by Mode)
A refresh operation in a stand-by mode will be described with reference to a timing chart shown in FIG. 14(b).
In the stand-by mode, the refresh control circuit 8H times a past time from a time of a last external request for access, so that if the past time becomes beyond a predetermined refresh time, then the refresh control circuit 8H outputs the refresh control signal REFB to start the self-refresh operation.
For example, in the stand-by mode, the refresh timer circuit 8G times the time interval for the self-refresh operations. At a timing given by the refresh timer circuit 8G, the refresh control circuit 8H causes the refresh address generator circuit 8J to generate the refresh row address R0 as the refresh address RADD. The address multiplexer 3 receives an input of the refresh row address R0 as the refresh address RADD and supplies the refresh row address R0 as the address MADE to the row decoder 60.
On the other hand, the refresh control circuit 8H outputs the refresh control signal REFB so as to cause the internal pulse generator circuit 10 to generate the row enable signal RE at an appropriate timing. The row decoder 60 receives an input of the refresh row address R0 as the address MADD from the address multiplexer 3 and selects a word line designated by the refresh row address R0 at a timing defined by the row enable signal RE for a predetermined period of time. Data signals of the memory cells connected to the selected word line are amplified by the sense amplifiers and then re-stored therein similarly to the above-described read mode. In the stand-by mode, the refresh is made for rows designated by refresh addresses sequentially generated by the refresh address generator circuit 8J in accordance with timings generated by the refresh timer circuit 8G.
For the SRAM, no limitation is present to the address skew externally supplied. There is no regulation for the skew on the specification. For the pseudo-SRAM having the basic element of DRAM, there is an inter-restriction to the timings of the internal circuits, wherein non-limitation to the skew does not guarantee the normal operation. For this reason, in case of the pseudo-SRAM, generally, an upper limit of the skew of the address externally supplied is regulated on the specification in order to provide the skew with a limitation. The user has to take into account that the skew of the address is kept not beyond the regulation value over the specification.
The presence of the limitation over specification to the skew of the address requires the user to set a timing by previously taking into account the skew. This provides a bar to the high rate performance. For example, in case of the page mode of the DRAM, the column addresses only are switched in accordance with the specification. The consideration of the skew for setting the timing of address makes it difficult to set a short cycle of address, whereby a high rate read operation as a characteristic of the page mode is no longer available.
The present invention has been made in view of the above-described circumstances. Accordingly, it is desirable to provide a non-synchronous semiconductor memory device configured as the pseudo-SRAM, which is, however, capable of relaxing the restriction to the skew of address and improving the read rate.